🚀 QuantumBoom

Demonstrating subthreshold scaling of a surface-code quantum memory on hardware whose native connectivity does not match the code remains a central challenge. We address this on IBM heavy-hex superconducting processors by co-designing the code embedding and control: a depth-minimizing SWAP-based "fold-unfold" embedding that uses bridge ancillas, together with robust, gap-aware dynamical decoupling (DD). On Heron-generation devices we perform anisotropic scaling from a uniform distance 3 code to anisotropic distance (dx,dz) = (3,5) and (5,3) codes. We find that increasing dz (dx) improves the protection of Z-basis (X-basis) logical states across multiple quantum error correction cycles. Even if global subthreshold code scaling for arbitrary logical initial states is not yet achieved, we argue that it is within reach with minor hardware improvements. We show that DD plays a major role: it suppresses coherent ZZ crosstalk and non-Markovian dephasing that accumulate during idle gaps on heavy-hex layouts, and it eliminates spurious subthreshold claims that arise when scaled codes without DD are compared against smaller codes with DD. To quantify performance, we derive an entanglement fidelity metric that is computed directly from X- and Z-basis logical-error data and provides per-cycle, SPAM-aware bounds. The entanglement fidelity metric reveals that widely used single-parameter fits used to compute suppression factors can mischaracterize or obscure code performance when their assumptions are violated; we identify the strong assumptions of stationarity, unitality, and negligible logical SPAM required for those fits to be valid and show that they do not hold for our data. Our results establish a concrete path to robust tests of subthreshold surface-code scaling under biased, non-Markovian noise by integrating QEC with optimized DD on non-native architectures.

Quantum error correction (QEC) is believed to be essential for the realization of large-scale quantum computers. However, due to the complexity of operating on the encoded `logical' qubits, understanding the physical principles for building fault-tolerant quantum devices and combining them into efficient architectures is an outstanding scientific challenge. Here we utilize reconfigurable arrays of up to 448 neutral atoms to implement all key elements of a universal, fault-tolerant quantum processing architecture and experimentally explore their underlying working mechanisms. We first employ surface codes to study how repeated QEC suppresses errors, demonstrating 2.14(13)x below-threshold performance in a four-round characterization circuit by leveraging atom loss detection and machine learning decoding. We then investigate logical entanglement using transversal gates and lattice surgery, and extend it to universal logic through transversal teleportation with 3D [[15,1,3]] codes, enabling arbitrary-angle synthesis with logarithmic overhead. Finally, we develop mid-circuit qubit re-use, increasing experimental cycle rates by two orders of magnitude and enabling deep-circuit protocols with dozens of logical qubits and hundreds of logical teleportations with [[7,1,3]] and high-rate [[16,6,4]] codes while maintaining constant internal entropy. Our experiments reveal key principles for efficient architecture design, involving the interplay between quantum logic and entropy removal, judiciously using physical entanglement in logic gates and magic state generation, and leveraging teleportations for universality and physical qubit reset. These results establish foundations for scalable, universal error-corrected processing and its practical implementation with neutral atom systems.

Quantum observables in the form of few-point correlators are the key to characterizing the dynamics of quantum many-body systems. In dynamics with fast entanglement generation, quantum observables generally become insensitive to the details of the underlying dynamics at long times due to the effects of scrambling. In experimental systems, repeated time-reversal protocols have been successfully implemented to restore sensitivities of quantum observables. Using a 103-qubit superconducting quantum processor, we characterize ergodic dynamics using the second-order out-of-time-order correlators, OTOC. In contrast to dynamics without time reversal, OTOC are observed to remain sensitive to the underlying dynamics at long time scales. Furthermore, by inserting Pauli operators during quantum evolution and randomizing the phases of Pauli strings in the Heisenberg picture, we observe substantial changes in OTOC values. This indicates that OTOC is dominated by constructive interference between Pauli strings that form large loops in configuration space. The observed interference mechanism endows OTOC with a high degree of classical simulation complexity, which culminates in a set of large-scale OTOC measurements exceeding the simulation capacity of known classical algorithms. Further supported by an example of Hamiltonian learning through OTOC, our results indicate a viable path to practical quantum advantage.

Quantum error correction (QEC) will be essential to achieve the accuracy needed for quantum computers to realise their full potential. The field has seen promising progress with demonstrations of early QEC and real-time decoded experiments. As quantum computers advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable and low-latency real-time decoding will be crucial to prevent the backlog problem, avoiding an exponential slowdown and maintaining a fast logical clock rate. Here, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor. We perform an 8-qubit stability experiment with up to decoding rounds and a mean decoding time per round below, showing that we avoid the backlog problem even on superconducting hardware with the strictest speed requirements. We observe logical error suppression as the number of decoding rounds is increased. We also implement and time a fast-feedback experiment demonstrating a decoding response time of for a total of measurement rounds. The decoder throughput and latency developed in this work, combined with continued device improvements, unlock the next generation of experiments that go beyond purely keeping logical qubits alive and into demonstrating building blocks of fault-tolerant computation, such as lattice surgery and magic state teleportation.

Quantum computers represent a transformative frontier in computational technology, promising exponential speedups beyond classical computing limits. IBM Quantum has led significant advancements in both hardware and software, providing access to quantum hardware via IBM Cloud® since 2016, achieving a milestone with the world's first accessible quantum computer. This article explores IBM's quantum computing journey, focusing on the development of practical quantum computers. We summarize the evolution and advancements of IBM Quantum's processors across generations, including their recent breakthrough surpassing the 1,000-qubit barrier. The paper reviews detailed performance metrics across various hardware, tracing their evolution over time and highlighting IBM Quantum's transition from the noisy intermediate-scale quantum (NISQ) computing era towards fault-tolerant quantum computing capabilities.

Advances in quantum hardware have begun the noisy intermediate-scale quantum (NISQ) computing era. A pressing question is: what architectures are best suited to take advantage of this new regime of quantum machines? We study various superconducting architectures including Google's Sycamore, IBM's Heavy-Hex, Rigetti's Aspen and Ankaa in addition to a proposed architecture we call bus next-nearest neighbor (busNNN). We evaluate these architectures using benchmarks based on the quantum approximate optimization algorithm (QAOA) which can solve certain quadratic unconstrained binary optimization (QUBO) problems. We also study compilation tools that target these architectures, which use either general heuristic or deterministic methods to map circuits onto a target topology defined by an architecture.

Quantum error correction provides a path to reach practical quantum computing by combining multiple physical qubits into a logical qubit, where the logical error rate is suppressed exponentially as more qubits are added. However, this exponential suppression only occurs if the physical error rate is below a critical threshold. In this work, we present two surface code memories operating below this threshold: a distance-7 code and a distance-5 code integrated with a real-time decoder. The logical error rate of our larger quantum memory is suppressed...Our results present device performance that, if scaled, could realize the operational requirements of large scale fault-tolerant quantum algorithms.